The proposed model will adopt the Memory In Processor paradigm to achieve closer integration of memory and the processing logic, thereby reducing the effect of ‘the processor memory gap’. Through the advances in Deep Sub- Micron technology, micro architecture and software & platform technologies, multi-core node architectures are becoming the order of the day and would guide supercomputing to the peta-flop goal.
The real impact of the problem falls on modelling the application for parallelism and designing an efficient compiler to manage massively parallel instruction issues. With increase in the number of cores this complexity increases and the compilers face the mammoth task of parallelizing the computations for execution. Although the multi-core technology drives us towards achieving the performance demanded by grand challenge applications, the perception of ‘Cost Effective Supercomputing’ (High Productivity Supercomputers) still remains far from realization.
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